Library ieee;
Use ieee.std_logic_1164.all;

ENTITY PC IS
PORT(PCin,PCout,Clk          : IN std_logic;
bidir 						 : INOUT std_logic_vector(15 downto 0));
END PC;


Architecture PC_reg of PC is 
SIGNAL PCval : std_logic_vector(15 downto 0);

begin
process(Clk)
begin
if rising_edge(Clk) then
	if PCin = '1' then
		PCval <= bidir;
	end if;
end if;
end process;
OutBus:
bidir <= PCval WHEN  PCout = '1' ELSE
		"ZZZZZZZZZZZZZZZZ";
end PC_reg;
